XDR Memory Architecture

Written by IT News on 7:32 AM

The Rambus XDR™ memory architecture is a total memory system solution that achieves an order of magnitude higher performance than today's standard memories while utilizing the fewest ICs. Perfect for compute and consumer electronics applications, a single, 2-byte wide, 4.0 GHz XDR DRAM component provides 8.0 GB/s of peak memory bandwidth.
The Rambus XDR™ memory interface architecture consists of four building block technologies: Differential Rambus Signaling Level (DRSL), Octal Data Rate (ODR), FlexPhase™ de-skewing circuitry, and Dynamic Point-to-Point (DPP) technology.

DRSL (Differential Rambus Signaling Level) is a low-voltage, low-power, differential signaling standard that enables the scalable multi-GHz, bi-directional, and point-to-point data busses that connect the XIO cell to XDR DRAM devices. XDR memory solutions also use the Rambus Signaling Level (RSL) standard developed originally for the RDRAM® memory interface, enabling up to 36 devices connected to the source-synchronous, bussed address and command signals.

ODR (Octal Data Rate) is a technology that transfers eight bits of data on each clock cycle, four times as many as today's state-of-the-art memory technologies that use DDR (Double Data Rate). XDR data rates are scalable to 8.0 GHz.

FlexPhase deskew circuits eliminate any systematic timing offsets between the bits of an XDR memory interface data bus. With a resolution of 2.5ps (at 3.2 GHz) and a maximum range of over 10 ns, the FlexPhase technology eliminates the need to match trace lengths on the board and package. FlexPhase also dynamically calibrates out on-chip clock skew, driver/receiver mismatch, and clock standing wave effects allowing lower system cost designs.

Dynamic Point-to-Point (DPP) technology maintains the signal integrity benefits of point-to-point signaling on the data bus while providing the flexibility of capacity expansions with module upgrades. Memory modules can be dynamically reconfigured to support diferrent data bus widths, allowing a memory controller with a fixed data bus width to connect to a variable number of modules.